Coarse gating of clock tree elements

摘要

Methods relating to distribution of a clock signal to logic devices of an integrated circuit. The method includes controlling, by a logic element, the distribution of a clock signal by a clock gater and distributing the clock signal by the clock gater to at least one first logic device, wherein the logic element allows the first clock gater to distribute the clock signal only when at least one first logic device requires the clock signal. An integrated circuit configured to perform such a method. Fabrication of such an integrated circuit.

主权项

1. An integrated circuit device, comprising:
a clock spine to distribute a clock signal; a first clock gater to receive the clock signal from the clock spine and distribute the clock signal; a logic element to control the distribution of the clock signal by the first clock gater; a plurality of second clock gaters, each to receive the clock signal from the first clock gater and distribute the clock signal; and a plurality of first logic devices, wherein each said first logic device receives the clock signal from one of the plurality of second clock gaters; wherein the logic element allows the first clock gater to distribute the clock signal only when at least one said first logic device requires the clock signal.