Integrated circuit including pulse control logic having shared gating control

摘要

An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal. The integrated circuit also includes a clock unit coupled to the one or more logic blocks and configured to generate a pulse clock signal formed using a chain of inverting logic gates. The clock unit may be further configured to provide the pulse clock signal to the clock distribution network. The clock unit may also include an enable input that is coupled to one input of one of the inverting logic gates. In addition, the clock unit may be configured to selectively enable and disable the pulse clock signal in response to an enable signal on the enable input.

主权项

1. An integrated circuit comprising:
one or more logic blocks, each including a clock distribution network configured to distribute a pulse clock signal; and a clock unit coupled to the one or more logic blocks and configured to generate the pulse clock signal that is formed using a chain of inverting logic gates, and to provide the pulse clock signal to the clock distribution network; wherein the clock unit includes an enable input that is coupled to one input of one of the inverting logic gates; wherein the clock unit includes a memory bypass input that is coupled to one input of another one of the inverting logic gates; and wherein the clock unit is configured to selectively enable and disable the pulse clock signal in response to an enable signal on the enable input.