Thin film transistor and fabricating method

摘要

A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.

主权项

1. A fabricating method for a thin-film transistor being used in a semiconductor panel consisting of a base, an intra-dielectric layer, at least one metal wire layer, at least one via layer and a surface, the intra-dielectric layer being stacked on the base, the at least one metal wire layer comprising a lowest metal wire layer and at least one metal wire with multiple metal wires being separated by corresponding intra-dielectric layers, one metal wire of the metal wires is a metal wire gate, the at least one via layer being stacked on the at least one metal wire layer and comprising at least one via with multiple vias being separated by corresponding intra-dielectric layers, wherein each via being stacked on the one metal wire of the metal wires, of which one via being stacked on the metal wire gate being a gate via, comprising steps of:
grinding the surface of the semiconductor panel; etching one via layer of the at least one via layer; stacking a dielectric layer on the semiconductor panel; stacking a semiconductor film layer on the dielectric layer; forming a conduct layer on the semiconductor film layer; defining a source zone and a drain zone each on a via of the vias that is adjacent to the gate via and connecting to the source zone, the drain zone and the gate via;
forming two generally U-shaped nano-wire channels in the gate via respectively connecting the source to the drain along a plane parallel with the base; and activating the conduct layer under the source and the drain.