VERIFICATION DEVICE OF SEMICONDUCTOR INTEGRATED CIRCUIT, VERIFICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND PROGRAM

摘要

PROBLEM TO BE SOLVED: To provide a verification method of semiconductor integrated circuits capable of achieving reduction in verification time.SOLUTION: In designing of the RTL description, the verification method of semiconductor integrated circuits models one memory into: a plurality of divided memories addressed by a part of address signals for designating addresses of the memory and having a capacity smaller than that of the memory; a first logical circuit for selecting a plurality of divided memories according to the residuals of the address signals; a delay circuit delaying the residuals of the address signals and outputting the delayed residuals of the address signals; and a second logical circuit selecting output from the divided memories in response to a signal from the delay circuit and defines it as output from the entire memory.