发明名称 |
HIGH-FREQUENCY SIGNAL PROCESSING DEVICE AND WIRELESS COMMUNICATION SYSTEM |
摘要 |
To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit. |
申请公布号 |
US2015078503(A1) |
申请公布日期 |
2015.03.19 |
申请号 |
US201414551518 |
申请日期 |
2014.11.24 |
申请人 |
Renesas Electronics Corporation |
发明人 |
Endo Ryo;Ueda Keisuke;Uozumi Toshiya |
分类号 |
H04L7/033;H03L7/099 |
主分类号 |
H04L7/033 |
代理机构 |
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代理人 |
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主权项 |
1. A high-frequency signal processing device, comprising:
a digital phase comparator unit inputting a feedback oscillation signal and a reference oscillation signal having a reference frequency, detecting a phase difference between the reference oscillation signal and the feedback oscillation signal, and also outputting a first digital signal representing the phase difference; a digital filter unit performing averaging processing on the first digital signal in synchronization with a first clock signal and outputting the processing result as a second digital signal; a digital control oscillator unit including an inductance element and plural capacitance elements each coupled to an oscillator node and outputting a carrier oscillation signal at the oscillator node by coupling the capacitance elements selectively to the oscillator node based on frequency setting information expressed by the second digital signal; a frequency divider unit outputting the feedback oscillation signal and the first clock signal by dividing the carrier oscillation signal; and a setting unit selecting a first clock frequency of the first clock signal from a plurality of options based on frequency band information of a standard to be used and controlling a frequency dividing ratio to be used in the frequency divider unit, based on the selected first clock frequency and a carrier frequency to be set among frequency bands of the standard. |
地址 |
Kawasaki-shi JP |