发明名称 SYSTEM AND METHOD FOR DATA SYNCHRONIZATION ACROSS DIGITAL DEVICE INTERFACES
摘要 A system for synchronizing and re-ordering data transmitted between first and second clock domains associated with first and second device interfaces, respectively, includes a splitter, an arbiter, a transaction manager, and a read data buffer. The splitter receives a parent read request from one or more data input ports of the first device interface and splits it into one or more read requests. The arbiter receives the one or more read requests and selects one of the read requests and transmits it to the transaction manager. The transaction manager allocates an entry to the read request and then the read request is transmitted to the read data buffer. Thereafter, the read data buffer transmits the read request to the second device interface and transmits received response data to the first device interface.
申请公布号 US2015081934(A1) 申请公布日期 2015.03.19
申请号 US201314028489 申请日期 2013.09.16
申请人 Gupta Vinay;Baruch Nir;Gur Amit 发明人 Gupta Vinay;Baruch Nir;Gur Amit
分类号 G06F5/16 主分类号 G06F5/16
代理机构 代理人
主权项 1. A system for synchronizing and re-ordering data transmitted between first and second clock domains associated with first and second device interfaces, respectively, comprising: an arbiter connected to one or more data input ports that receives one or more read requests, and selects at least one read request from the one or more read requests based on a predetermined criteria, wherein the one or more data input ports are associated with the first device interface; a transaction manager, connected to the arbiter, that includes one or more entries organized as one or more linked lists, each linked list corresponding to at least one of the one or more data input ports, wherein the transaction manager allocates a first entry of the one of the entries to the selected read request, wherein the first entry is associated with a first linked list of the one or more linked lists corresponding to the selected read request, determines the first entry associated with a toggle signal, generates a read pointer when the first entry is an initial entry of the first linked list, invalidates the initial entry after generating the read pointer, and designates an entry subsequent to the initial entry as the initial entry; an asynchronous first-in-first-out (FIFO) module connected to the arbiter and the transaction manager for appending an entry identifier corresponding to the first entry; and a read data buffer connected to the asynchronous FIFO module and the transaction manager for receiving the selected read request, generating a tag corresponding to the first entry, appending the tag to the selected read request, transmitting the selected read request to the second device interface, receiving a response data from the second device interface, mapping the response data with the corresponding read request entry identifier using the tag associated with the response data and a mapping table that includes a mapping between the one or more entry identifiers and corresponding tags generated by the read data buffer, transmitting the toggle signal corresponding to the first entry, and transmitting the response data corresponding to the first entry to the first device interface.
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