SAR-ADC WITH SPILT DUAL CAPACITIVE ARRAY

摘要

The present invention relates to a SAR-ADC including a split dual capacitive array. The SAR-ADC includes a dual capacitor array including a first capacitor for array converting upper bits in n bits and a second capacitor array for converting lower bits; a comparator comparing a level signal output from the first capacitor array and a level signal output from the second capacitor array; and a SAR logic circuit converting an analog input voltage to the n bit digital signal by using the compared result, wherein the first capacitor array includes a 1-1 capacitor unit and a 1-2 capacitor unit, and the second capacitor array includes a 2-1 capacitor unit and a 2-2 capacitor array, and each of the capacitor units includes a plurality of capacitors connected in parallel.