Versatile communication system and method of implementation using heterogeneous integration

摘要

A communication system front-end architecture and a method of fabricating same are disclosed in which a diverse set of semiconductor technologies and device types (including CMOS, SiGe CMOS, InP HBTs (heterojunction bipolar transistors), InP HEMTs (high electron mobility transistors), GaN HEMTs, SiC devices, any number from a diverse set of MEMS sensors and actuators, and potentially photonics) is merged onto a single silicon, or other material substrate to thereby enable the development of smaller, lighter, and higher performance systems.

主权项

1. A communication system front-end architecture in which a diverse set of semiconductor technologies and device types are integrated onto a single material substrate, the front-end architecture comprising:
a tunable microelectromechanical systems (MEMS) filter/duplexer formed from aluminum nitride (AlN) resonators for filtered, bi-directional communication over an antenna, a first bank of gallium nitride (GaN) switches connected between the filter/duplexer (receive channel), power amplifier (transmit channel) and the antenna, a silicon-germanium (SiGe), indium phosphide (InP) or gallium arsenide (GaAs) high electron mobility transistor (HEMT) tunable low noise amplifier (LNA), a second bank of GaN switches connected between the filter/duplexer and the low noise amplifier, a tunable microelectromechanical systems (MEMS) image filter formed from AlN resonators and connected to the low noise amplifier, a SiGe mixer for combining or mixing frequencies, the mixer including a SiGe phase locked loop (PLL) control system with a voltage controlled oscillator (VCO), a SiGe bipolar junction and complementary metal-oxide-semiconductor (BiCMOS) or silicon complementary metal-oxide-semiconductor (CMOS) or an indium phosphide (InP) analog to digital converter (ADC) and digital to analog converter (DAC), a silicon (Si) field programmable gate array (FPGA) for reprogramming the front-end architecture for different applications, the field programmable gate array being connected to the analog to digital converter and the digital to analog converter, a SiGe or InP tunable pre-amplifier connected to the mixer, a plurality of high-Q passives implemented using three level thick metallization on a fused-silica substrate and being connected to an output of the tunable pre-amplifier, a GaN reconfigurable power amplifier connected to the high-Q passives and the first bank of GaN switches, and a mixed-signal (analog and digital signals) control circuit, based on FPGA, silicon microcontroller or custom digital integrated circuit is connected to all tunable/switched devices within the system including mixer, tunable image filter, the analog to digital converter and the digital to analog converter, the tunable pre-amplifier and the digital control, to the tunable low noise amplifier, the high-Q passives, the first and the second banks of GaN switches, the reconfigurable power amplifier, and antenna.