具有镀覆引线之积体电路封装系统及其制造方法;INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLATED LEADS AND METHOD OF MANUFACTURE THEREOF

摘要

一种积体电路封装系统及其制造方法包含：提供具有未处理引线的引线架；在该未处理引线之顶部表面上沉积蚀刻遮罩，该未处理引线具有该蚀刻遮罩与该顶部表面之未遮罩部分；连接积体电路晶粒至该未处理引线；以封装件主体包覆该引线架，该未处理引线之该顶部表面从该封装件主体暴露出来；形成可侧焊引线，包含形成沟槽在该未处理引线中，该沟槽形成在该蚀刻遮罩之一部分之下包含在该沟槽上方形成该蚀刻遮罩之悬伸物；移除该蚀刻遮罩；以及沉积电镀在该可侧焊引线上。; depositing an etch mask on a top surface of the unprocessed leads, the unprocessed leads having the etch mask and an unmasked portions of the top surface; connecting an integrated circuit die to the unprocessed leads; encapsulating with a package body the leadframe, the top surface of the unprocessed leads exposed from the package body; forming side-solderable leads including forming a groove in the unprocessed leads, the groove formed under a portion of the etch mask including forming an overhang of the etch mask over the groove; removing the etch mask; and depositing a plating on the side-solderable leads.