发明名称 |
ISA EXTENSIONS FOR SYNCHRONOUS COALESCED ACCESSES |
摘要 |
Global synchrony changes the way computers can be programmed. A new class of ISA level instructions (the globally-synchronous load-store) of the present invention is presented. In the context of multiple load-store machines, the globally synchronous load- store architecture allows the programmer to think about a collection of independent load-store machines as a single load-store machine. These ISA instructions may be applied to a distributed matrix transpose or other data that exhibit a high degree of data non-locality and difficulty in efficiently parallelizing on modern computer system architectures. Included in the new ISA instructions are a setup instruction and a synchronous coalescing access instruction ("sea"). The setup instruction configures a head processor to set up a global map that corresponds processor data contiguously to the memory. The "sea" instruction configures processors to block processor threads until respective times on a global clock, derived from the global map, to access the memory. |
申请公布号 |
WO2015034802(A1) |
申请公布日期 |
2015.03.12 |
申请号 |
WO2014US53648 |
申请日期 |
2014.09.02 |
申请人 |
MASSACHUSETTS INSTITUTE OF TECHNOLOGY |
发明人 |
WHELIHAN, DAVID, JOSEPH;KELTCHER, PAUL, STANTON |
分类号 |
G06F9/52;G06F9/30;G06F13/16 |
主分类号 |
G06F9/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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