发明名称 POWER SUPPLY SYSTEMS AND METHODS
摘要 One example of generating a clock signal via an oscillator system includes increasing a first comparison voltage at a first comparison node from a first magnitude to a second magnitude in response to a clock signal. A second comparison voltage is increased at a second comparison node from the first magnitude to the second magnitude in response to the clock signal. The clock signal changes state in response to the second comparison voltage increasing to a magnitude that is greater than the first comparison voltage. The first comparison voltage decreases from the second magnitude to the first magnitude in response to the clock signal. The second comparison voltage decreases from the second magnitude to the first magnitude in response to the clock signal. The clock signal changes state in response to the second comparison voltage decreasing to a magnitude that is less than the first comparison voltage.
申请公布号 US2015069987(A1) 申请公布日期 2015.03.12
申请号 US201414517695 申请日期 2014.10.17
申请人 Tan F. Dong;Yi Kwang M. 发明人 Tan F. Dong;Yi Kwang M.
分类号 H02M1/08;H03K5/135;H02M3/158 主分类号 H02M1/08
代理机构 代理人
主权项 1. A method for generating a clock signal via an oscillator system, the method comprising: increasing a first comparison voltage at a first comparison node of a comparator from a first magnitude to a second magnitude in response to a first state of a clock signal that is output from the comparator; increasing a second comparison voltage at a second comparison node of the comparator from approximately the first magnitude to greater than the second magnitude in response to the first state of the clock signal; changing the clock signal from the first state to a second state in response to the second comparison voltage increasing to a magnitude that is greater than the first comparison voltage; decreasing the first comparison voltage from the second magnitude to the first magnitude in response to the second state of the clock signal; decreasing a second comparison voltage from approximately the second magnitude to less than the first magnitude in response to the second state of the clock signal; and changing the clock signal from the second state to the first state in response to the second comparison voltage decreasing to a magnitude that is less than the first comparison voltage.
地址 Irvine CA US