| 摘要 |
This invention addresses the problem of using a vertical transistor, namely a surrounding gate transistor (SGT), to provide a semiconductor device that constitutes part of a CMOS NAND circuit and has a small surface area. In said NAND circuit, which comprises a plurality of MOS transistors arranged in m rows and n columns, each of said MOS transistors is formed on a flat silicon layer formed on top of a substrate, wherein a drain, a gate, and a source are arranged vertically, the gate is structured so as to surround a silicon pillar, the flat silicon layer comprises a first activated region that has a first conductivity type and a second activated region that has a second conductivity type, and said regions are connected to each other via a silicon layer formed at the surface of the flat silicon layer, thereby providing a semiconductor device that constitutes part of a NAND circuit and has a reduced surface area. |
