| 摘要 |
The invention relates to a pMOS transistor having low threshold voltage, which pMOS transistor is provided with a p-doped semiconductor substrate (12), which has a top face (16), an n-doped trough region (14), which is formed within the semiconductor substrate (12) and which extends to the top face (16) of the semiconductor substrate (12), a p-doped source connection region (24) and a p-doped drain connection region (26), which are both formed within the n-doped trough region (14) on the top face (16) of the semiconductor substrate (12), and a channel region (18), which is arranged on the top face (16) of the semiconductor substrate (12) within the n-doped trough region (14) between the source and drain connection regions (24, 26) and has a source-side and a drain-side end (68, 74). The channel region (18) has a dopant profile that - as observed in the extension between the source and the drain connection regions (24, 26) - has either a substantially homogeneous or a non-uniform, in particular decreasing or increasing dopant concentration and is formed by the thermal diffusion of ions of at least one dopant of an ion implantation zone with masking (34, 34', 34'', 40, 60), which has at least one masking region (36, 36', 66, 78) located at least partially within the channel region (18), and a gate insulation layer (20) having a gate electrode (22) thereon, said gate insulation layer extending over the channel region (18) and being arranged on the top face (16) of the semiconductor substrate (12). |
