| 摘要 |
1,251,709. Checking circuits. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 28 May, 1969 [31 May, 1968], No. 26981/69. Heading G4H. A logical circuit LC is checked by selecting a pattern of digital signals PW 1 from a read only store DM by a selector SO, passing them through the circuit LC and feeding the result to a result register AR where in the case of at least one pattern, if the result is correct, the contents of the whole register select the address of the next pattern and, if the result is incorrect, the contents select the address of an alarm word. The pattern of signals is preceded by an address part which is transferred direct from the buffer register BR to position 1 of the result register AR formed of flip-flops. On Fig. 1 word W 1 has a pattern PW 1 and an address part AW 1 of 01 and the result sent to position 2 can be a "1" or a "0", which is one digit of a multi-digit result of a logical operation (e.g. addition, majority detection, parity check). Thus register AR can hold 010 or 011. If 010 is held, an error indicating word F is selected and an alarm L triggered. If 011 is held, word W2 is selected and the process repeated. Only simple errors are taken into account, a double error could produce a "1" at position 2. In a modification (Fig. 3, not shown) an extra digit is added to each word to indicate whether or not the result selects the address of the next word. If not, only the address part of the word selects the next word. The circuit LC has two outputs thus indicating for possible addresses: 00,01,10,11. In another modification (Figs. 4 and 5, not shown) each word has an identifying bit and a change bit in which the pattern is passed through circuit LC as before, a bit is calculated from the identifying and change bits, and this calculated bit compared with the identifying bit of the selected word to trigger an alarm or proceed with the new word depending on the comparison. In another modification (Figs. 6 and 7, not shown) each word has a first additional bit and a second additional bit whereby the second additional bit is held in a comparator, and the first additional bit of the next word must be equal thereto if no error has occurred. |
