INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC

摘要

An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.

主权项

1. A method to fabricate an integrated circuit comprising field effect transistors (FETs) at least some of which comprise a part of random access memory (RAM) and logic devices, comprising:
providing a substrate having an N+ type layer; forming a buffer layer on a portion of the N+ type layer; forming a P type region on the buffer layer, the P type layer having a thickness that is disposed within the N+ type layer; forming an insulator layer overlying the N+ type layer having a silicon layer overlying the insulator layer; forming a first deep trench isolation structure extending through the silicon layer, the insulating layer and the buffer layer, and into the N+ type layer to a depth that is greater than a depth at which the P type layer is disposed, the first deep trench isolation structure abutting a first edge of the P type layer; forming a dynamic RAM FET in the silicon layer connected with a conductive node of a trench capacitor that is formed to extend into the N+ type layer, the N+ type layer being a plate electrode of the trench capacitor, forming a first logic/static RAM FET in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic/static RAM FET; and forming a first contact through the silicon layer and the insulating layer to electrically connect to the N+ type layer and a second contact through the silicon layer and the insulating layer to electrically connect to the P type region.