CLOCK SYNCHRONIZER FOR ALIGNING REMOTE DEVICES

摘要

Various aspects of the present disclosure are directed apparatuses and methods including a first phase locked loop (PLL) circuit and a second PLL circuit. The first PLL circuit receives a carrier signal that is transmitted over a communications channel from a non-synchronous device, and generates a PLL-PLL control signal. The second PLL circuit receives a stable reference-oscillation signal, and, in response to the PLL-PLL control signal indicating a frequency offset, adjusts a fractional divider ratio of the second PLL circuit. The first PLL circuit and the second PLL circuit are configured to produce an output frequency signal that is synchronous to the carrier signal.

主权项

1. An apparatus comprising:
(a) a first phase locked loop (PLL) circuit configured and arranged to
receive a carrier signal that is transmitted over a communications channel from a non-synchronous device,generate a PLL-PLL control signal, andobserve a mode in which the carrier signal has inadequate signal quality; (b) a second PLL circuit configured and arranged to
receive a stable reference-oscillation signal, andadjust, in response to the PLL-PLL control signal indicating a frequency offset, a fractional divider ratio of the second PLL circuit; and (c) the first PLL circuit and the second PLL circuit being further configured and arranged to produce an output frequency signal that is synchronous to the carrier signal and, in response to the mode being observed by the first PLL circuit, to suspend further adjustment of the PLL-PLL control signal, wherein the output frequency signal is synchronized to the carrier signal and concurrent with the mode being determined by the first PLL circuit, synchronization is maintained via operation of the second PLL circuit.