METHOD AND APPARATUS FOR SUPPRESSING A DETERMINISTIC CLOCK JITTER

摘要

A method for generating an output clock comprising: detecting a timing difference between a first input clock and a second input clock to generate a phase error signal; generating a masked phase error signal by masking the phase error signal based on a deterministic jitter indicator signal; generating an oscillator control signal by filtering the masked phase error signal; and generating the output clock in accordance with the oscillator control signal.

主权项

1. An apparatus comprising:
a phase detector for receiving a first input clock and a second input clock and generating a phase error signal representing a timing difference between the first input clock and the second input clock; a mask circuit for masking the phase error signal to generate a masked phase error signal in accordance with a deterministic jitter indicator signal that indicates a deterministic jitter of the first input clock; a loop filter for filtering the masked phase error signal to generate an oscillator control signal; and a control oscillator for generating an output clock in accordance with a control of the oscillator control signal.