RADIATION-HARDENED STORAGE UNIT

摘要

A radiation-hardened storage unit, including a basic storage unit, a redundant storage unit, and a two-way feedback unit. The basic storage unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The first PMOS transistor and the second PMOS transistor are read-out access transistors. The third PMOS transistor and the fourth PMOS transistor are write-in access transistors. The redundant storage unit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The fifth PMOS transistor and the sixth PMOS transistor are read-out access transistors. The seventh PMOS transistor and the eighth PMOS transistor are write-in access transistors. The two-way feedback unit is configured to form a feedback path between the storage node and the redundant storage node.

主权项

1. A radiation-hardened storage unit, comprising
a) a basic storage unit; b) a redundant storage unit; and c) a two-way feedback unit;wherein
said basic storage unit comprises a first PMOS transistor (501), a second PMOS transistor (502), a third PMOS transistor (503), and a fourth PMOS transistor (504); said first PMOS transistor (501) and said second PMOS transistor (502) are read-out access transistors; a source of said first PMOS transistor (501) is connected to a read selecting word line (516), a gate thereof is connected to a storage node (Q1), and a drain thereof is connected to a first read-out bit line (517); a source of said second PMOS transistor (502) is connected to said read selecting word line (516), a gate thereof is connected to an inverting storage node (Q1N), and a drain thereof is connected to a second read-out bit line (518); said third PMOS transistor (503) and said fourth PMOS transistor (504) are write-in access transistors; a source of said third PMOS transistor (503) is connected to said storage node (Q1), a gate thereof is connected to a write selecting word line (513), and a drain thereof is connected to a first write-in bit line (514); a source of said fourth PMOS transistor (504) is connected to said inverting storage node (Q1N), a gate thereof is connected to said write selecting word line (513), and a drain thereof is connected to a second write-in bit line (515); said redundant storage unit comprises a fifth PMOS transistor (505), a sixth PMOS transistor (506), a seventh PMOS transistor (507), and an eighth PMOS transistor (508); said fifth PMOS transistor (505) and said sixth PMOS transistor (506) are read-out access transistors; a source of said fifth PMOS transistor (505) is connected to said read selecting word line (516), a gate thereof is connected to a redundant storage node (Q2), and a drain thereof is connected to said first read-out bit line (517); a source of said sixth PMOS transistor (506) is connected to said read selecting word line (516), a gate thereof is connected to an inverting redundant storage node (Q2N), and a drain thereof is connected to a second read-out bit line(518); said seventh PMOS transistor (507) and said eighth PMOS transistor (508) are write-in access transistors; a source of said seventh PMOS transistor (507) is connected to said redundant storage node (Q2), a gate thereof is connected to said write selecting word line (513), and a drain thereof is connected to said first write-in bit line (514); a source of said eighth PMOS transistor (508) is connected to said inverting redundant storage node (Q2N), a gate thereof is connected to said write selecting word line (513), and a drain thereof is connected to said second write-in bit line (515); and said two-way feedback unit is configured to form a feedback path between said storage node (Q1) and said redundant storage node (Q2), and further to form a feedback path between said inverting storage node (Q1N) and said inverting redundant storage node (Q2N).