Voltage conversion circuit and voltage conversion method

摘要

A voltage conversion circuit comprises a first and a second output (O1, O2) which are configured to have an electric load (LD) connected therebetween, wherein an output signal between the first and a second output (O1, O2) is generated in response to a pulse-width modulated clock signal (PWM). The circuit further comprises a forward branch (FWD) being configured to generate an output voltage (VDC) at the first output (O1) depending on a control signal. A feedback branch (FBK) comprises a comparison circuit (CC) being configured to generate the control signal. The feedback branch (FBK) is configured to provide a first potential corresponding to a voltage (VSINK) at a second output (O2) to a comparison input (CI) of the comparison circuit (CC) during a first sensing period which corresponds to at least a part of a period of a first state of the clock signal (PWM) and to provide a second potential derived from the voltage (VSINK) at a second output (O2) by means of a first charge store (C1) to the comparison input (CI) during a second sensing period which corresponds to a part of a period of a second state of the clock signal (PWM).

主权项

1. A voltage conversion circuit comprising a first output and a second output which are configured to have an electric load connected there between, the voltage conversion circuit being configured to generate an output signal between the first output and the second output in response to a pulse-width modulated clock signal, and further comprising:
a forward branch configured to generate an output voltage at the first output depending on a control signal; and a feedback branch comprising a comparison circuit to generate the control signal, comprising a first switch coupling the second output to a comparison input of the comparison circuit, and comprising a first charge store with a first end directly connected to the second output and with a second end coupled to the comparison input via a second switch, the feedback branch being configured to provide a first potential corresponding to a voltage at the second output to the comparison input by switchably coupling, via the first switch, the second output to the comparison input during a first sensing period which corresponds to at least a part of a period of a first state of the pulse-width modulated clock signal, and to provide a second potential derived from the voltage at the second output by the first charge store to the comparison input by switchably coupling, via the second switch, the second end of the first charge store to the comparison input during a second sensing period which corresponds to a part of a period of a second state of the pulse-width modulated clock signal.