Systems and methods for idle clock insertion based power control

摘要

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In one particular case, a system is disclosed that includes a first data processing circuit operable to apply a data detection algorithm to a data input synchronous to a first clock, and a second data processing circuit operable to apply a subsequent data processing algorithm to an output derived from the first data processing circuit synchronous to a second clock, and an idle time enforcement circuit operable to modify an average frequency of at least one of the first clock and the second clock.

主权项

1. A data processing system, the data processing system comprising:
a first data processing circuit operable to apply a data detection algorithm to a data input synchronous to a first clock; a second data processing circuit operable to apply a subsequent data processing algorithm to an output derived from the first data processing circuit synchronous to a second clock; and an idle time enforcement circuit operable to determine that the first data processing circuit and the second data processing circuit are concurrently operational, and based at least in part on determining that the first data processing circuit and the second data processing circuit are concurrently operational, to modify an average frequency of at least one of the first clock and the second clock by suppressing one cycle for each N clock cycles of at least one of the first clock and the second clock.