METHOD AND SYSTEM OF TESTING SEMICONDUCTOR MEMORY

摘要

A method of testing a semiconductor memory includes generating a logical value of a test pattern through an algorithm pattern generator included in a field programmable gate array. The generated logical value is programmed in a DUT under the control of a DQ signal responding to a DQ enable signal that is generated from automatic test equipment and is then transferred to the field programmable gate array. The programmed logical value is captured from the DUT under the control the DQ signal. The generated logical value is compared with the captured logical value. Whether the DUT is defective is determined according to a result of the comparison. The DQ enable signal is applied to a time point different from a time point when a SYNC clock for synchronizing the automatic test equipment with the field programmable gate array is applied.

主权项

1. A method of testing a semiconductor memory, the method comprising:
generating a logical value of a test pattern through an algorithm pattern generator included in a field programmable gate array (FPGA); programming the generated logical value in a device-under-test (DUT) under control of a DQ signal responding to a DQ enable signal that is generated from an automatic test equipment and is then transferred to the FPGA; capturing the programmed logical value from the DUT under control of the DQ signal; and comparing the generated logical value with the captured logical value and determining whether the DUT is defective according to a result of the comparison, wherein the DQ enable signal is applied at a time point different from a time point when a SYNC clock for synchronizing the automatic test equipment with the FPGA is applied.