HIERARCHICAL WRITE-COMBINING CACHE COHERENCE

摘要

A method, computer program product, and system is described that enforces a release consistency with special accesses sequentially consistent (RCsc) memory model and executes release synchronization instructions such as a StRel event without tracking an outstanding store event through a memory hierarchy, while efficiently using bandwidth resources. What is also described is the decoupling of a store event from an ordering of the store event with respect to a RCsc memory model. The description also includes a set of hierarchical read-only cache and write-only combining buffers that coalesce stores from different parts of the system. In addition, a pool component maintains partial order of received store events and release synchronization events to avoid content addressable memory (CAM) structures, full cache flushes, as well as direct write-throughs to memory. The approach improves the performance of both global and local synchronization events and reduces overhead in maintaining write-only combining buffers.

主权项

1. A method comprising:
receiving a memory event; when the memory event is a store event, the method further comprises:
writing a first data to a write-only, level n cache, where n is an integer representing a level of cache hierarchy;writing, to a level n pool, a store entry that includes an address of the first data in the level n cache, wherein the level n pool maintains a partial order among the store entry, a prior received store entry, and a release marker entry; andwhen a release marker is present, ordering the store entry in the level n pool to follow a most-recent release marker; and when the memory event is a load event, the method further comprises:
searching a read-only, level n cache for a second data; anddetermining whether the second data is present in a corresponding write-only, level n cache.