Integrate Circuit With Nanowires

摘要

The present disclosure provides an integrated circuit (IC). The IC includes a substrate having a metal-oxide-semiconductor (MOS) region. The IC further includes first gate, source and drain regions, having a first length, and second gate, source and drain regions, having a second length. A first nanowire set is disposed in the first gate region, the first nanowire set including a nanowire having a first diameter and connecting to a feature in the first source region and a feature in the first drain region. A second nanowire set is disposed in the second gate region, the second nanowire set including a nanowire having a second diameter and connecting to a feature in the second source region and a feature in the second drain region. The diameters are such that if the first length is greater than the second length, the first diameter is less than the second diameter, and vice versa.

主权项

1. An integrated circuit (IC) comprising:
a substrate having a metal-oxide-semiconductor (MOS) region; first gate, source and drain regions of a first device in the MOS region, wherein the first gate region has a first length; a first nanowire set disposed in the first gate region, the first nanowire set including a nanowire having a first diameter and connecting to a first feature in the first source region and a second feature in the first drain region; second gate, source and drain regions of a second device in the MOS region, wherein the second gate region has a second length; and a second nanowire set disposed in the second gate region, the second nanowire set including a nanowire having a second diameter and connecting to a third feature in the second source region and a fourth feature in the second drain region, wherein the first diameter is different from the second diameter.