DYNAMIC MEMORY CELL REPLACEMENT USING COLUMN REDUNDANCY

摘要

A memory chip comprises a main memory array having a plurality of memory columns, a redundancy memory column associated with the main memory array, and a hit logic circuitry configured to generate a plurality of hit logic signals by a plurality of hit logic units in the hit logic circuitry to enable dynamic replacement of a defective memory cell in one of the memory columns for dynamic replacement by the redundancy memory column when the memory array is in operation.

主权项

1. A method performed with a memory chip having a memory array having a plurality of memory columns, comprising:
generating a plurality of hit logic signals by a plurality of hit logic units in a hit logic circuitry associated with the memory array to enable dynamic replacement a defective memory cell in one of the memory columns; designating the memory column containing the defective memory cell for replacement if the defective memory cell is identified; replacing the designated memory column with a redundancy memory column by dynamically reasserting the address of the designated column to the redundancy memory column when the memory array is in operation; wherein the dynamic replacement of the designated column having the defective memory cell with the redundancy column is completed before the next read/write operation is performed on the memory array.