| 发明名称 | Structure, structure and method of latch-up immunity for high and low voltage integrated circuits | ||
| 摘要 | Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic. | ||
| 申请公布号 | US8963158(B2) | 申请公布日期 | 2015.02.24 |
| 申请号 | US201313946259 | 申请日期 | 2013.07.19 |
| 申请人 | International Business Machines Corporation | 发明人 | Voldman Steven H. |
| 分类号 | H01L27/108;H01L27/092;H01L21/8238;H01L29/10;H01L29/78;H01L29/06;H01L29/08 | 主分类号 | H01L27/108 |
| 代理机构 | Roberts Mlotkowski Safran & Cole, P.C. | 代理人 | LeStrange Michael;Roberts Mlotkowski Safran & Cole, P.C. |
| 主权项 | 1. A structure comprising a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic, wherein at least one downwardly extending lateral edge of the diffused N-Tub and a downwardly extending lateral edge of the retrograde N-well, on a same side, are recessed with respect to one another, and wherein the P-wafer directly contacts a bottom surface of the retrograde N-well. | ||
| 地址 | Armonk NY US | ||