发明名称 Method of fabricating semiconductor device
摘要 A method of fabricating a semiconductor device includes forming a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the surface of the substrate within a gate trench, removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth, and removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth.
申请公布号 US8962455(B2) 申请公布日期 2015.02.24
申请号 US201313920181 申请日期 2013.06.18
申请人 Samsung Electronics Co., Ltd. 发明人 Choi Sang-Hyun;Noh Jin-Ho;Son Yoon-Ho;Chung Dae-Hyuk;Hwang In-Seak;Park Tae-Joon;Hwang Tae-Ho
分类号 H01L21/36;H01L21/768;H01L21/28;H01L29/78;H01L29/423;H01L27/108 主分类号 H01L21/36
代理机构 Ellsworth IP Group, PLLC 代理人 Ellsworth IP Group, PLLC
主权项 1. A method of fabricating a semiconductor device, the method comprising: forming a gate trench in a substrate; forming a gate insulating layer on bottom and side surfaces of the gate trench; forming a gate barrier material layer and a gate electrode material layer on bottom and side surfaces of the gate insulating layer and a top surface of the substrate; removing the gate barrier material layer and the gate electrode material layer from the substrate to form a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the top surface of the substrate within the gate trench; removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth; removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth; and forming a gate capping layer to cover the gate barrier layer and the gate electrode and fill the gate trench.
地址 Suwon-si KR