发明名称 WIRING SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE
摘要 A wiring substrate includes: a substrate layer made of glass or silicon and including: a first surface formed with a first hole; and a second surface formed with a second hole and being opposite to the first surface, wherein the first hole is communicated with the second hole; a connection pad formed in the second hole; a first wiring layer formed in the first hole and electrically connected to the connection pad; a first insulation layer formed on the first surface of the substrate layer to cover the first wiring layer; and a second wiring layer formed on the first insulation layer and electrically connected to the first wiring layer. A diameter of the first hole is gradually decreased from the first surface toward the second surface, and a diameter of the second hole is gradually decreased from the second surface toward the first surface.
申请公布号 US2015048505(A1) 申请公布日期 2015.02.19
申请号 US201414527079 申请日期 2014.10.29
申请人 Shinko Electric Industries Co., Ltd. 发明人 KUNIMOTO Yuji;KOIZUMI Naoyuki
分类号 H05K1/11;H05K1/03;H05K1/02;H01L23/00 主分类号 H05K1/11
代理机构 代理人
主权项 1. A wiring substrate comprising: a substrate, a material of the substrate consisting of of glass or silicon, the substrate having: a first surface formed with a first hole; anda second surface formed with a second hole and being opposite to the first surface, the first hole being communicated with the second hole, and the second surface of the substrate is a mounting surface on which a semiconductor chip is to be mounted; a connection pad formed in the second hole; a first wiring layer formed in the first hole and electrically connected to the connection pad; a first insulation layer formed on the first surface of the substrate to cover the first wiring layer, the first insulting layer being made of a resin material; a second wiring layer formed on the first insulation layer and electrically connected to the first wiring layer; a plurality of insulation layers and a plurality of wiring layers being alternately arranged to form a stack on the first surface side of the substrate; and a solder resist layer formed on a surface of the stack opposite to the substrate, wherein a diameter of the first hole is gradually decreased from the first surface toward the second surface, and a diameter of the second hole is gradually decreased from the second surface toward the first surface.
地址 Nagano-shi JP