MEMORY DEVICE AND METHOD OF PERFORMING ACCESS OPERATIONS WITHIN SUCH A MEMORY DEVICE

摘要

A memory device includes an array of memory cells arranged as a plurality of rows and columns, a plurality of word lines, each word line being coupled to an associated row of memory cells, and a plurality of bit lines, each bit line being coupled to an associated column of memory cells. Access circuitry is coupled to the word lines and the bit lines in order to perform access operations in respect of selected memory cells within the array. Control circuitry controls operation of the access circuitry and includes self-timed path (STP) delay circuitry. The control circuitry employs the delay indication when controlling the access circuitry to perform said access operations. Voltage supply control circuitry switches the voltage supply to at least one portion of the STP delay circuitry between a peripheral voltage supply and an array voltage supply dependent on a control signal.

主权项

1. A memory device comprising:
an array of memory cells arranged as a plurality of rows and columns, the array operating in an array voltage domain with an array voltage supply; a plurality of word lines, each word line being coupled to an associated row of memory cells; a plurality of bit lines, each bit line being coupled to an associated column of memory cells; access circuitry coupled to the plurality of word lines and the plurality of bit lines in order to perform access operations in respect of selected memory cells within the array, at least a part of the access circuitry operating in a peripheral voltage domain with a peripheral voltage supply; control circuitry configure to control operation of the access circuitry, the control circuitry including self-timed path (STP) delay circuitry configured to generate a delay indication indicative of an access timing delay associated with accessing the memory cells, the control circuitry employing said delay indication when controlling the access circuitry to perform said access operations; and voltage supply control circuitry associated with at least one portion of the STP delay circuitry and configured to switch the voltage supply to said at least one portion of the STP delay circuitry between said peripheral voltage supply and said array voltage supply dependent on a control signal set having regard to the voltage levels of said array voltage supply and said peripheral voltage supply.