| 摘要 |
The delay line degradation protection architecture as build-in ring oscillation apparatus includes a two gates logical circuit, a buffer, a clock input buffer and a delay lock loop circuit. The two gates logical circuit receives a clock enable signal, specific mode signal, and delayed clock output signal. The two gates logical circuit performs a logical operating on the clock enable signal, the specific mode signal and the delayed clock output signal for generating a mode selecting signal. The buffer generates a feedback signal according to the mode selecting signal and a control signal. The clock input buffer decides whether to transport the input clock signal to an output end of the clock input buffer or not according to the feedback signal. The delay lock loop circuit generates the delayed clock output signal. A frequency of the feedback signal is adjusted according to the control signal. |
| 主权项 |
1. A delay line ring oscillation apparatus, comprising:
a two gates logical circuit, having three input ends and an output end, two of the three input ends respectively receiving a clock enable signal and a specific mode signal, and the third input end further receiving a delayed clock output signal or a fine delayed output signal, the two gates logical circuit performing a logical operating on the clock enable signal, the specific mode signal and one of the delayed clock output signal and the fine delayed output signal for generating a mode selecting signal on the output end of the two gates logical circuit; a buffer, receiving the mode selecting signal and generating a feedback signal according to the mode selecting signal and a control signal; a clock input buffer, receiving the feedback signal and a input clock signal, the clock input buffer deciding whether to transport the input clock signal to an output end of the clock input buffer or not according to the feedback signal; and a delay lock loop circuit, receiving and delaying the signal on the output end of the clock input buffer for generating the delayed clock output signal, wherein, a frequency of the feedback signal is adjusted according to the control signal. |
