| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock regeneration circuit which can generate stabilized regeneration clock signals at a high speed. <P>SOLUTION: The clock regeneration circuit comprises a first sample-and-hold circuit (312) which samples and holds a first clock signal in synchronism with input data, a second sample-and-hold circuit (313) which inputs a second clock signal having the same frequency as that of the first clock signal and a phase different from that of the first clock signal by 90°, and samples and holds a second clock signal in synchronism with the input data, a first mixer circuit (314) which mixes the first clock signal and an output signal from the second sample-and-hold circuit (313), a second mixer circuit (315) which mixes the second clock signal and an output signal from the first sample-and-hold circuit, and a subtractor (316) which outputs a regeneration clock signal by subtracting an output signal of the first mixer circuit from an output signal of the second mixer circuit. <P>COPYRIGHT: (C)2012,JPO&INPIT</p> |
