发明名称 Laminate stacked capacitor, circuit substrate with laminate stacked capacitor and semiconductor apparatus with laminate stacked capacitor
摘要 A method of manufacturing a capacitor includes forming a first ceramic film on a first base made of a metal, forming a second ceramic film on a second base made of a metal, forming a first copper electrode pattern and a first copper via-plug on a surface of one of the first and second ceramic films, the electrode pattern and the via-plug being separate from each other, bonding the first and second ceramic films together with the first electrode pattern and the via-plug therebetween, by applying a pulsed voltage between the first base and the second base while the first base and the second base are pressed so that the first ceramic film and the second ceramic film are pressed on each other, and removing the second base.
申请公布号 US8957499(B2) 申请公布日期 2015.02.17
申请号 US201113228091 申请日期 2011.09.08
申请人 Fujitsu Limited 发明人 Imanaka Yoshihiko;Amada Hideyuki;Kumasaka Fumiaki
分类号 H01L29/00;H01G4/30;B82Y30/00;B82Y40/00;H01G4/232;H05K1/16;H05K1/02 主分类号 H01L29/00
代理机构 Kratz, Quintos & Hanson, LLP 代理人 Kratz, Quintos & Hanson, LLP
主权项 1. A capacitor, comprising: a metal base; a plurality of capacitor dielectric layers made of a ceramic and disposed on top of one another on the base, the capacitor dielectric layers including: a first capacitor dielectric layer,a second capacitor dielectric layer adjacent to the first capacitor dielectric layer, anda third capacitor dielectric layer adjacent to the second capacitor dielectric layer at the opposite side to the first capacitor dielectric layer; a first copper electrode pattern and a first copper via-plug with a space therebetween between the first capacitor dielectric layer and the second capacitor dielectric layer; a second copper electrode pattern and a fourth copper via-plug with a space therebetween between the second capacitor dielectric layer and the third capacitor dielectric layer; and a second via-plug and a third via-plug in the second capacitor dielectric layer, wherein the first copper electrode pattern opposes the second copper electrode pattern with the second capacitor dielectric layer therebetween,the first copper via-plug is electrically connected to the second copper electrode pattern through the third via-plug,the fourth copper via-plug is electrically connected to the first copper electrode pattern through the second via-plug, andthe first copper electrode pattern and the second copper electrode pattern are electrically connected to a first terminal and a second terminal, respectively.
地址 Kawasaki JP