发明名称 TORN WRITE MITIGATION
摘要 A torn write mitigation circuit determines if a write operation on a memory is being executed during power loss time or around the power loss time. If the write operation is being executed during the power loss time or around the power loss time, the torn write mitigation circuit makes torn write data and metadata to be stored in a nonvolatile cache. The torn write data includes data degraded as a result of power loss or remained not modifiable. The metadata includes the torn write data.
申请公布号 KR20150017672(A) 申请公布日期 2015.02.17
申请号 KR20140099744 申请日期 2014.08.04
申请人 发明人
分类号 G06F12/08;G06F12/16 主分类号 G06F12/08
代理机构 代理人
主权项
地址
您可能感兴趣的专利