发明名称 Semiconductor device and manufacturing method of semiconductor device
摘要 According to one embodiment, the semiconductor device in the embodiment has an assembly substrate, a semiconductor chip, and a jointing layer. The semiconductor chip is joined to the assembly substrate via the jointing layer. An intervening diffusion barrier layer may be interposed between the chip and jointing layer. The jointing layer is an alloy layer mainly made of any metal selected from Sn, Zn and In or an alloy of Sn, Zn and In, and any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V or an alloy of any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V and any metal selected from Sn, Zn and In, where the alloy has a higher melting temperature than that of Sn, Zn and In or an alloy of Sn, Zn and/or In.
申请公布号 US8957522(B2) 申请公布日期 2015.02.17
申请号 US201313787526 申请日期 2013.03.06
申请人 Kabushiki Kaisha Toshiba 发明人 Sasaki Yo;Hiratsuka Daisuke;Yamamoto Atsushi;Kodani Kazuya;Hisazato Yuuji;Matsumura Hitoshi
分类号 H01L23/52;H01L23/532;H01L21/768;H01L21/58;H01L23/00 主分类号 H01L23/52
代理机构 Patterson & Sheridan, LLP 代理人 Patterson & Sheridan, LLP
主权项 1. A semiconductor device comprising: an assembly substrate; a semiconductor chip joined to the assembly substrate through a jointing layer that is between the assembly substrate and the semiconductor chip the jointing layer including an alloy comprising: at least one of Sn, Zn and In, and at least one of Cu, Ni, Ag, Cr, Zr, Ti and V; and a soft metal layer between the jointing layer and the semiconductor chip and including any metal selected from Cu, Al, Zn and Ag, wherein the jointing layer includes at least two phases of the alloy.
地址 Tokyo JP