发明名称 Semiconductor memory device and method of controlling the same
摘要 A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
申请公布号 US8959411(B2) 申请公布日期 2015.02.17
申请号 US201414231140 申请日期 2014.03.31
申请人 Kabushiki Kaisha Toshiba 发明人 Kanno Shinichi;Uchikawa Hironori
分类号 H03M13/00;G06F11/10;H03M13/29;H03M13/03 主分类号 H03M13/00
代理机构 Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A storage device comprising: a nonvolatile semiconductor memory configured to store a plurality of first block correcting codes to respectively correct first errors in a plurality of first data blocks, a second block correcting code to correct second errors in a second data block which includes the first data blocks; a first error corrector configured to correct the first errors; and a second error corrector configured to correct the second errors, a circuit scale of the second error corrector being larger than a circuit scale of the first error corrector, wherein in a case where the first error occurs, a first error correction processing is performed by using the first block correcting codes, in a case where the second error occurs, a second error correction processing is performed by using the second block correcting code, and an error correction capability of the second error correction processing is higher than an error correction capability of the first error correction processing.
地址 Minato-ku JP