发明名称 INRUSH CURRENT SUPPRESSION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To cope with an inrush current and a large current at a normal time even when there are variations in characteristics of an FET used in parallel.SOLUTION: An inrush current suppression circuit includes: an inrush current suppression controller that monitors an input voltage as an output voltage of a DC power supply for supplying a power supply with an apparatus to control a driving signal according to the monitored input voltage; a plurality of FETs that split output currents of the DC power supply to connect them in parallel to become each drain current; a current detection circuit for detecting each drain current of the plurality of FETs; and a FET controller that individually controls each gate voltage of the plurality of FETs in response to the driving signal so as to drive a second FET of the plurality of FETs to drive each of the plurality of FETs in a stepwise manner when the drain current of a first FET of the plurality of FETs detected by the current detection circuit exceeds a preset first threshold.
申请公布号 JP2015033224(A) 申请公布日期 2015.02.16
申请号 JP20130161247 申请日期 2013.08.02
申请人 HITACHI LTD 发明人 OHASHI MAKOTO;IWANAGA YUZO;NOBUMOTO KOICHI
分类号 H02J1/00;G05F1/10;H02H9/02 主分类号 H02J1/00
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