A buffer circuit includes a buffering unit suitable for buffering an input signal and outputting an output signal and a feedback control unit suitable for adjusting a slew rate of the input signal in response to the output signal.
申请公布号
US2015042394(A1)
申请公布日期
2015.02.12
申请号
US201314082850
申请日期
2013.11.18
申请人
SK hynix Inc.
发明人
HWANG Tae-Jin
分类号
H03K6/04;H03K6/02
主分类号
H03K6/04
代理机构
代理人
主权项
1. A buffer circuit comprising:
a buffering unit suitable for buffering an input signal; and a feedback control unit suitable for adjusting a slew rate of the input signal by receiving an output signal fed back from the buffering unit.
