发明名称 Shallow Trench Isolation Area Having Buried Capacitor
摘要 A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area.
申请公布号 US2015041949(A1) 申请公布日期 2015.02.12
申请号 US201414521302 申请日期 2014.10.22
申请人 Infineon Technologies AG 发明人 Terletzki Hartmud
分类号 H01L27/06;H01L21/8234;H01L21/762;H01L49/02;H01L29/06 主分类号 H01L27/06
代理机构 代理人
主权项 1. A semiconductor chip comprising: a substrate comprising a surface; an active transistor region and a substrate contact region disposed at the substrate; a shallow trench isolation (STI) area disposed at the surface and disposed at least partially between the active transistor region and the substrate contact region; and at least one capacitor at least partially buried in the STI area, wherein the at least one capacitor comprises a plurality of capacitors arranged such that the capacitors are completely buried within the STI area, plates of the capacitors are disposed in a direction perpendicular to the surface of the substrate, and the capacitors are connected to each other in a line-to-line configuration.
地址 Neubiberg DE