| 发明名称 | Semiconductor storage device | ||
| 摘要 | A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates.;In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well. | ||
| 申请公布号 | US8953371(B2) | 申请公布日期 | 2015.02.10 |
| 申请号 | US201213425121 | 申请日期 | 2012.03.20 |
| 申请人 | Kabushiki Kaisha Toshiba | 发明人 | Shiino Yasuhiro;Irieda Shigefumi;Nakai Kenri;Takahashi Eietsu;Ueno Koki |
| 分类号 | G11C11/34;G11C11/56;G11C16/06;G11C16/04;G11C16/34 | 主分类号 | G11C11/34 |
| 代理机构 | Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. | 代理人 | Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
| 主权项 | 1. A semiconductor storage device, comprising: a plurality of memory cells each having a control gate that are formed on a well; and a control circuit that applies a voltage to the well and the control gates, wherein in an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erase voltage that rises stepwise to the well and then applies a second pulse wave of a second erase voltage to the well, the second erase voltage is a square wave, and a step difference of the first erase voltage that rises stepwise is smaller than a difference between the second erase voltage of the second pulse wave and a final value of the first erase voltage that rises stepwise. | ||
| 地址 | Tokyo JP | ||