Wafer level package and fabrication method

摘要

A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.

主权项

1. An electronic package comprising:
an integrated circuit chip comprising:
a chip top surface;a chip bottom surface opposite the chip top surface;a plurality of chip side surfaces extending between the chip top surface and the chip bottom surface; anda bond pad on the chip bottom surface; a dielectric layer comprising:
a dielectric layer top surface;a dielectric layer bottom surface opposite the dielectric layer top surface; anda plurality of dielectric layer side surfaces extending between the dielectric layer top surface and the dielectric layer bottom surface,where the dielectric layer top surface is coupled to the chip bottom surface; a conductive via extending through the dielectric layer and coupled to the bond pad of the integrated circuit chip; a trace coupled to the conductive via and coupled to the dielectric layer; and encapsulant encapsulating the chip top surface and chip side surfaces and coupled to the dielectric layer top surface.