| 发明名称 | Semiconductor memory device | ||
| 摘要 | According to one embodiment, a semiconductor memory device includes n (n being a natural number of 2 or more) data retention circuits connected to a data input/output terminal; n buses connected respectively to the n data retention circuits; m×n data latch circuits connected to the buses, with m (m being a natural number of 2 or more) data latch circuits being connected per one of the buses; and a selection circuit configured to simultaneously perform data transfer from/to the data retention circuits for a plurality of the data latch circuits in units of a group including the plurality of the data latch circuits, the data latch circuits being divided into the groups so that not all the data latch circuits connected to the same bus are included in the same group. | ||
| 申请公布号 | US8953390(B2) | 申请公布日期 | 2015.02.10 |
| 申请号 | US201314014944 | 申请日期 | 2013.08.30 |
| 申请人 | Kabushiki Kaisha Toshiba | 发明人 | Ogawa Masatsugu;Takagiwa Teruo |
| 分类号 | G11C7/10 | 主分类号 | G11C7/10 |
| 代理机构 | Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. | 代理人 | Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
| 主权项 | 1. A semiconductor memory device comprising: n (n being a natural number of 2 or more) data retention circuits connected to a data input/output terminal; n buses connected respectively to the n data retention circuits; m×n data latch circuits connected to the buses, with m (m being a natural number of 2 or more) data latch circuits being connected per one of the buses; and a selection circuit configured to simultaneously perform data transfer from/to the data retention circuits for a plurality of the data latch circuits in units of a group including the plurality of the data latch circuits, the data latch circuits being divided into the groups so that not all the data latch circuits connected to the same bus are included in the same group. | ||
| 地址 | Minato-ku JP | ||