Method of Improving Timing Critical Cells For Physical Design In The Presence Of Local Placement Congestion

摘要

Optimizing circuits having a congested placement with a timing critical placement map includes identifying critical circuit components in the placement map and determining failing circuit components in the placement map; determining “non-critical” circuit components safe to be moved; removing selected non critical from the placement map; and optimizing the critical circuit components in a new partial placement image of said map; and reinserting the “non-critical” circuit components back into said placement image. The optimization is performed by circuit transformation operating in congested regions of the placement image enabling cell insertion and modifications that increase cell size.

主权项

1. A method for optimizing circuits having a congested placement with a timing critical placement map comprising:
using a computer, determining non-critical circuit components safe to be moved wherein non-critical circuit components are circuits in which a change to its physical placement will not degrade the timing below an acceptable threshold or introduce a new timing violation; removing all non-critical circuit components from said timing critical placement map to generate a new partial placement map; optimizing critical circuit components in said new partial placement map free of all of said non-critical circuit components wherein said critical circuit components are a set of circuit components that are not non-critical circuit components; inserting new circuit components to replace failing critical circuit components; and reinserting all of said non-critical circuit components that were previously removed from said timing critical placement map into said new partial placement map.