发明名称 Method and Apparatus for Integrated Circuit Mask Patterning
摘要 Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.
申请公布号 US2015040081(A1) 申请公布日期 2015.02.05
申请号 US201313956962 申请日期 2013.08.01
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Huang Chin-Min;Chen Bo-Han;Yeh Lun-Wen;Yang Shun-Shing;Chang Chia-Cheng;Tsay Chern-Shyan;Lai Chien Wen;Lin Hua-Tai
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址 Hsin-Chu TW