| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To obtain an appropriate bit clock stably with a small calculation amount. <P>SOLUTION: When a count-down pulse DOWN is output from a logic circuit 15 and the counting down of a count value C results in a borrow, an U/D counter 16 included in a bit clock synchronization circuit outputs a borrow signal BORROW, or when a count-up pulse UP is output and the counting up of the count value C results in a carry, the U/D counter 16 outputs a carry signal CARRY. When a borrow signal BORROW is output from the U/D counter 16, an oscillation signal frequency division number is decremented, or when a carry signal CARRY is output from the U/D counter 16, the oscillation signal frequency division number is incremented. <P>COPYRIGHT: (C)2013,JPO&INPIT</p> |
