Coherency controller and method for data hazard handling for copending data access requests

摘要

A data processing system that manages data hazards at a coherency controller and not at an initiator device is disclosed. Write requests are processed in a two part form, such that a first part is transmitted and when the coherency controller has space to accept data, the data and a state of the data prior to a write are sent as a second part of a write request. When there are copending reads and writes to the same address, writes are stalled by not responding to the first part of a write request and snoop requests received to the address are processed regardless of the fact that the write is pending. When the pending read has completed, the coherency controller will respond to the first part of the write request and the initiator device will complete the write by sending the data and a state indicator following the snoop.

主权项

1. A coherency controller for maintaining data coherency of data stored in a data processing apparatus comprising at least one initiator device and at least one recipient device, said coherency controller comprising:
at least one port for receiving data access requests from said at least one initiator device and for transmitting said data access requests and snoop requests to at least one of said at least one initiator device and said at least one recipient device; a buffer configured to store pending data access requests; snoop request generating circuitry configured to generate said snoop requests in response to said pending data access requests, said snoop requests determining whether data to be accessed is stored locally in one or more of said at least one initiator device and said at least one recipient device; and coherency control circuitry, responsive to receipt of a first part of a write request comprising an indication that a write is to be performed to an address for which a read request is pending, configured to stall said write request by not responding to said first part of said write request until after the pending read request has completed, wherein said coherency control circuitry is responsive to receipt of a signal indicating completion of said read request to respond to said first part of said write request; and said coherency control circuitry, responsive to receipt of a second part of said write request received after the response to said first part of said write request and comprising said data and an indication of a state of said data prior to said write request, to write said data to said at least one recipient device.