发明名称 Multilayer capacitor
摘要 A multilayer capacitor that can suppress electrostrictive vibration without material constraint and with applicability to various structures, including general-purpose structures. A multilayer capacitor has: an element body formed of dielectric ceramic; and a plurality of internal electrodes disposed inside the element body such that the internal electrodes are stacked with ceramic layers sandwiched therebetween. The multilayer capacitor is provided with a capacitor area which includes the plurality of internal electrodes and a first suppression area and a second suppression area for reducing electrostriction caused by the plurality of internal electrodes so as to suppress noise. The first suppression area is adjacent to the capacitor area and the thickness of the second suppression area is determined according to the arrangement of the plurality of internal electrodes.
申请公布号 US8947850(B2) 申请公布日期 2015.02.03
申请号 US201213546729 申请日期 2012.07.11
申请人 TDK Corporation 发明人 Togashi Masaaki
分类号 H01G4/30;H01G4/015;H01G2/22;H01G2/24 主分类号 H01G4/30
代理机构 Oliff PLC 代理人 Oliff PLC
主权项 1. A multilayer capacitor comprising: an element body formed of dielectric ceramic; a plurality of internal electrodes disposed inside the element body such that the internal electrodes are stacked with ceramic layers sandwiched therebetween; and a pair of terminal electrodes provided on an outer surface of the element body and connected to the internal electrodes, wherein: a capacitor area which includes the plurality of internal electrodes and a suppression area for reducing electrostriction caused by the plurality of internal electrodes to suppress noise are formed, at least part of the suppression area is adjacent to the capacitor area, a thickness of the suppression area is determined according to an arrangement of the plurality of internal electrodes, the thickness being determined to satisfy the following expressions: α/β≦650α=We*n/d (We: electrode width, n: number of stacked electrodes, d: inter-electrode distance); andβ=T/W (T: suppression area thickness, W: element body width), a marking for indicating a position of the capacitor area relative to the element body is provided on the outer surface of the element body, and the marking is formed by wiring out a plurality of marking internal electrodes to the outer surface at a portion where the paired terminal electrodes are not formed, the marking is integrated with ends of the plurality of marking internal electrodes exposed in the outer surface.
地址 Tokyo JP