Semiconductor package with through silicon vias

摘要

The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns.

主权项

1. A semiconductor device package, comprising:
a substrate with through silicon plugs extending from a first surface of the substrate to a second surface opposite to the first surface, wherein the substrate is a silicon substrate or a silicon-on-insulator (SOI) substrate, and wherein sidewalls of the one or more through silicon plugs are lined with an isolation layer and a first copper barrier layer, and wherein the through silicon plugs are filled with a first copper layer, wherein the through silicon plugs have first ends and second ends; a first conductive contact pad formed over one or more of the first ends of a first subset of the through silicon plugs, wherein the first subset of the through silicon plugs include a plurality of through silicon plugs; a second conductive contact pad formed over one or more of the first ends of a second subset of the through silicon plugs, wherein the second conductive contact pad is separated from the first conductive contact pad by a gap; a semiconductor chip disposed on the first conductive contact pad, wherein the semiconductor chip is coupled to the second conductive contact pad by a bond wire, and wherein a substantial entirety of a surface of the semiconductor chip is in contact with the first conductive contact pad; and a molding material disposed over the first conductive contact pad, the second conductive contact pad, and the semiconductor chip, wherein the molding material is free of being laterally confined, and wherein both sidewall surfaces of the first and second conductive contact pads are covered by the molding material.