Multiple clock domain cycle skipping utilizing optimal mask to minimize voltage noise

摘要

Implementations of the present disclosure involve an apparatus and/or method for providing one or more clock signals that include a skipped clock cycle to a portion of a computing system. The skipped cycle clock signals may be changed by the computing system during operation of the system by altering masks applied to a global clock signal. However, the flexibility to alter various skipped cycle clock signals may introduce noise or signal disruptions within the system. Thus, the present disclosure may also involve an apparatus and/or method for managing the altering of the clock cycle skipping masks to manage the voltage noise introduced into the system by the adjustment of the operating frequency of the portions of the system. In one embodiment, the method includes prioritizing or otherwise ordering the bits of the masks applied to the global clock signal to attempt to prevent similar bits from being altered simultaneously.

主权项

1. A method of power savings on a processor, the method comprising:
providing a first skipped cycle timing signal to the processor, wherein the first skipped cycle timing signal includes a gated representation of a global timing signal and a first symbol, wherein the first symbol comprises a plurality of non-asserted bits in a plurality of bit positions and an asserted bit in at least one other bit position, wherein the plurality of non-asserted bits correspond to a skipped cycle of the global timing signal; receiving a request to adjust the first skipped cycle timing signal in response to a plurality of factors related to processor conditions; selecting a bit position from the plurality of bit positions of non-asserted bits; generating a second symbol in response to the request; and providing a second skipped cycle timing signal to the processor, wherein the second skipped cycle timing signal includes a gated representation of the global timing signal and the second symbol such that the non-asserted bits of the second symbol correspond to a plurality of skipped cycles of the global timing signal; wherein the selection of the bit position from the plurality of bit positions of non-asserted bits is based at least on a voltage noise generated from providing the second skipped cycle timing signal to the processor.