| 摘要 |
<p>A nonvolatile memory array is organized into a plurality of interleaving even and odd blocks. When a block is selected for operation, a set of word line voltages are delivered to the block of word lines by space-efficient decoding circuits and scheme. The plurality of blocks is organized into an array of pairs of adjacent odd and even blocks. A first voltage bus allows all even blocks access to the set of word line voltages. A second voltage bus allows all odd blocks access to the set of word line voltages. A decoder for selection is provided for each pair of adjacent even and odd blocks. Selecting a block is effected by selecting the pair of adjacent even and odd blocks containing the selected block, and supplying the set of word line voltages only to the selected block, which is one of the even or odd block in the selected pair.</p> |
