SIZE ADJUSTING CACHES BASED ON PROCESSOR POWER MODE

摘要

As a processor enters selected low-power modes, a cache is flushed of data by writing data stored at the cache to other levels of a memory hierarchy. The flushing of the cache allows the size of the cache to be reduced without suffering an additional performance penalty of writing the data at the reduced cache locations to the memory hierarchy. Accordingly, when the cache exits the selected low-power modes, it is sized to a minimum size by setting the number of ways of the cache to a minimum number. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache.

主权项

1. A method, comprising:
during operation of a processor, flushing a cache in response to the processor entering a first low-power state; setting a number of ways of a cache to a first size in response to the processor exiting a first low-power state; and adjusting the number of ways of the cache from the first size to a second size by changing a number of ways of each set of the cache available to store data in response to identifying a first level of processing activity at the processor.