| 摘要 |
<p>The present invention relates to a counter-based multi-cycle processor controller and, more specifically, to a counter-based multi-cycle processor controller. The counter-based multi-cycle processor controller includes: an instruction fetch unit which decodes a first counter value to generate an instruction fetch signal, and fetches an instruction at the instruction fetch signal; a data path control signal generation unit which generates a second counter value, decodes the second counter value and the fetched instruction to generate a data path control signal; and a counter reset signal generation unit which generates a first counter reset signal or a second counter reset signal, which is determined according to a counter value corresponding to each cycle stage of the fetched instruction.</p> |
